Standards

/ˌpiː eɪ ˈɛn/

n. "Small-scale network interconnecting personal electronics within 10m range via Bluetooth or USB unlike WiFi LAN."

PAN, short for Personal Area Network, connects devices in individual workspace (~10m range) using wireless (Bluetooth, Zigbee, UWB) or wired (USB, Firewire) links without infrastructure routers—smartphone+watch+earbuds form piconet while USB hub links printer/keyboard forming wired PAN. Contrasts WiFi BSS requiring AP with direct peer-to-peer topology serving single user vs multi-user LAN/WAN.

Key characteristics of PAN include: Limited Range 1-10m ideal for personal devices (phone, wearables, peripherals); No Infrastructure ad-hoc connections without central AP/router; Low Power WPANs (<1mW avg) enable battery operation unlike WiFi 100mW+; Data Rates 1-25Mbps (Bluetooth BR/LE) vs gigabit LAN; Peer-to-Peer direct device addressing without IP stack.

Conceptual example of PAN usage:

/* Bluetooth PAN profile - NAP/GN (Network Access Point/Group ad-hoc)
struct bt_pan_network {
    uint8_t nap_role;        // 0=GN, 1=NAP 
    bdaddr_t local_addr;
    bdaddr_t remote_addr;
};

int bt_pan_connect(bdaddr_t *remote) {
    // L2CAP connection to PAN-U/L channel
    struct l2cap_conn *conn = l2cap_connect(remote, PSM_PANU);
    
    // NAP negotiation: BNEP (Bluetooth Network Encapsulation Protocol)
    bnep_setup(conn, ETH_P_IP, 1500);  // IP over PAN MTU
    
    // Data transfer: Ethernet II frames over BNEP
    send_eth_frame("192.168.1.2", IP_PROTO_UDP, sensor_data, 128);
    
    return bnep_session_active();
}

Conceptually, PAN creates personal bubble network linking smartphone+smartwatch+wireless earbuds via Bluetooth piconet—master phone synchronizes health data while USB PAN shares printer without WiFi AP. WPANs enable IoT wearables (Zigbee heart monitor) communicating directly vs infrastructure WLAN, conserving battery via TDD duty cycling unlike always-on SerDes links; UWB PANs deliver cm-level positioning for AR glasses tracking hand gestures within 10m personal space.

/ˈwaɪ faɪ/

n. "IEEE 802.11 WLAN standard using OFDM/CSMA-CA for infrastructure/IBSS connectivity unlike Bluetooth piconets."

WiFi, short for Wireless Fidelity, implements IEEE 802.11 protocols across 2.4/5/6GHz bands (WiFi 7=802.11be=46Gbps via 320MHz channels + MLO), creating infrastructure BSS (AP+STA) or ad-hoc IBSS networks with CSMA/CA medium contention and 802.11r/k/v fast roaming. Contrasts Bluetooth's master-slave FHSS by using OFDM/OFDM6E with MU-MIMO+OFDMA serving 1024 QA-MOD QAM clients simultaneously, secured via WPA3-SAE (dragonfly handshake) unlike BLE's ECDH.

Key characteristics of WiFi include: OFDM Subcarriers 234/996/3.3k (20/80/320MHz) with 4096-QAM; MU-MIMO 16x16 spatial streams unlike Bluetooth SISO; OFDMA Resource Units partition channels for IoT; Target Wake Time (TWT) schedules STA sleep cycles; WPA3 Personal (SAE) + Enterprise (802.1X) authentication; 6GHz UNII-5/8 clean spectrum (WiFi 6E/7).

Conceptual example of WiFi usage:

# WiFi 6 AP monitor mode packet capture (Scapy)
from scapy.all import *

# Filter 802.11ax HE (WiFi 6) beacons
def packet_handler(pkt):
    if pkt.haslayer(Dot11Beacon):
        if 'HE_CAP' in pkt:
            he_mcs = pkt[Dot11HECapabilities].he_mcs_nss
            print(f"WiFi 6 AP: {pkt.info.decode()} 1024-QAM: {he_mcs}")
        ssid = pkt.info.decode()
        channel = ord(pkt[Dot11Elt:3].info)
        print(f"BSS: {ssid} ch{channel}")

# Sniff 5GHz WiFi 6E channels
sniff(iface="wlan0mon", prn=packet_handler, filter="type mgt subtype beacon")

# WPA3 SAE handshake capture for analysis
# Pairwise Master Key: PMK = SAE(authentication)
# 4-way handshake derives PTK/GTK

Conceptually, WiFi transforms wired Ethernet into wireless LAN via AP broadcasting beacons—STA contend via CSMA/CA while WiFi 7's Multi-Link Operation bonds 5+6GHz for 10Gbps effective throughput. Stress-tested via packet generators unlike SerDes BERT, with spectrum analyzers confirming PRBS-like OFDM subcarrier flatness; powers enterprise WLAN where Bluetooth handles personal area and USB4 docks, enabling seamless WPA2/WPA3 roaming across 100+ APs.

/ˈbluːtuːθ/

n. "Short-range wireless PAN standard using FHSS in 2.4GHz ISM band for piconet/scatternet device pairing."

Bluetooth, short for Bluetooth, enables cable replacement via frequency-hopping spread spectrum (FHSS) across 79 x 1MHz channels (2.402-2.480GHz), forming piconets (1 master/7 slaves) with TDD/TDMA access and LFSR-derived hopping sequences for interference immunity. Classic (BR/EDR=3Mbps GFSK) handles audio streaming while Bluetooth Low Energy (LE=2Mbps, BLE 5.4=4.4Mbps coded PHY) targets IoT sensors with 1.6-188ms intervals—pairs via LAPU authentication using 128-bit keys unlike WiFi's WPA3.

Key characteristics of Bluetooth include: FHSS 1600 hops/sec across 79/40 LE channels evading 2.4GHz WiFi interference; Piconet Topology 1M:7S with 7.5ms slots (625μs classic); Adaptive Frequency Hopping (AFH) blacklists jammed channels; LE PHY GFSK/PSK/M=4 up to 2.4Mbps with 125/250Kbps coded PHYs; Secure Pairing legacy (PIN), Secure Simple (OOD), LE Secure Connections (P-256 ECDH).

Conceptual example of Bluetooth usage:

/* BLE 5.0 Central scanning for heart rate sensor */
#include <bluetooth/bluetooth.h>
#include <bluetooth/hci.h>
#include <bluetooth/hci_lib.h>

int main() {
    int dd = hci_open_dev(0);  // HCI device 0
    hci_filter_clear(&nf);
    hci_filter_set_ptype(HCI_SCANO_REQ_IT, &nf);  // LE scan
    setsockopt(dd, SOL_HCI, HCI_FILTER, &nf, sizeof(nf));
    
    // Scan 10.24s interval for BLE advertisements
    struct hci_dev_info di;
    hci_devinfo(dd, &di);
    le_set_scan_enable(dd, 0x01, 0x01, 100);  // Active scan
    
    // Parse HR measurement (0x180D service)
    uint8_t hr_value = advertisement;  // BPM in 8-bit field
    printf("Heart Rate: %d BPM\n", hr_value);
    
    hci_close_dev(dd);
    return 0;
}

Conceptually, Bluetooth creates personal area networks via master-slave hopping synchronized to clock—audio A2DP streams over classic BR/EDR while BLE GATT services expose sensors to smartphones without WiFi infrastructure. Mesh topologies (BLE 5.0+) relay via advertiser/relay nodes, stress-tested with PRBS-like packet error rates unlike SerDes BERT validation; powers wireless keyboards, TWS earbuds, and fitness trackers where <1mW average power trumps USB4's gigabit throughput.

/bɪst/

n. "Self-contained test circuitry embedded within ICs generating PRBS patterns to validate SerDes and logic post-manufacturing."

BIST, short for Built-In Self-Test, integrates pattern generators, response analyzers, and control logic directly into silicon enabling at-speed functional testing without external ATE—crucial for validating SerDes CTLE/DFE convergence, memory arrays, and random logic using LFSR-driven patterns with MISR (Multiple Input Signature Register) compaction. LBIST (Logic BIST) stresses datapaths while MBIST (Memory BIST) marches/march13N patterns through SRAM detecting stuck-at/coupling faults.

Key characteristics of BIST include: On-Chip Pattern Generation via PRPG (LFSR/LFSR+ROM) eliminates external vector loading; Response Compaction condenses millions test bits into 32-512b signature via MISR; At-Speed Testing clocked at mission frequency unlike slow-scan; Self-Repair fuses redundant rows in MBIST; Test Time predictable cycles vs ATPG vector count.

Conceptual example of BIST usage:

// LBIST Controller + PRPG + MISR for SerDes core
module bist_controller (
  input clk, rst_n, test_mode,
  input [31:0] scan_enable,
  output reg [511:0] signature
);
  reg [6:0] lfsr_state;
  wire prbs_bit;
  reg misr_clk;
  
  // PRPG (LFSR-127 for logic BIST)
  always @(posedge clk) begin
    if (test_mode)
      lfsr_state <= {lfsr_state[5:0], lfsr_state ^ lfsr_state};
  end
  assign prbs_bit = lfsr_state;
  
  // MISR signature compaction (512b poly x^512 + x^11 + x^2 + 1)
  always @(posedge misr_clk) begin
    signature <= {signature[510:0], signature ^ signature ^ prbs_bit};
  end
  
  // Run 10M cycles, compare golden_signature
  // Pass: signature == 512'hDEADBEEF... (precomputed fault-free)
  // Fail: Mismatch indicates stuck-at fault
endmodule

Conceptually, BIST transforms passive silicon into active diagnostic engine—PRPG floods DUT with PRBS, MISR digests responses into compact signature verified against golden reference at power-on or field diagnostics. Production ATE triggers BIST execution in <100ms (vs hours ATPG), enabling 99.9% fault coverage for USB4 PHYs where external probing hits physical limits; self-repair fuses boost yield 5%+ while runtime BIST enables graceful degradation in AI accelerators.

/ˈsɜːr dɛs/

n. "Parallel-to-serial transceiver pair enabling high-speed chip-to-chip communication over minimal pins."

SerDes, short for Serializer/Deserializer, converts wide parallel data buses (32-128 bits) into high-speed serial streams over 1-4 differential pairs for PCIe, USB4, and Ethernet backplanes, with TX PISO (Parallel-In Serial-Out) clocking bits via PLL while RX SIPO (Serial-In Parallel-Out) recovers data/clock using CDR. Integrates CTLE, DFE, and LFSR-driven PRBS generators for 112Gbps+ PAM4 links with 1e-6 pre-FEC BER.

Key characteristics of SerDes include: Parallel-to-Serial Conversion reduces 64 PCB traces to 4 differential pairs; Clock Data Recovery extracts embedded timing from serial stream; Equalization Stack combines CTLE (high-freq boost) + DFE (post-cursor cancel); 8b/10b, 64b/66b, or 256b/257b encoding ensures DC balance; Retimers/Redrivers extend reach beyond 30dB loss.

Conceptual example of SerDes usage:

// 32:1 SerDes TX serializer (simplified)
module serdes_tx_32to1 (
  input clk_32x,          // 32GHz for 1Gbps serial
  input [31:0] parallel_in,
  output reg serial_out
);
  reg [4:0] bit_cnt = 0;
  reg [31:0] data_reg;
  
  always @(posedge clk_32x) begin
    if (bit_cnt == 31) begin
      data_reg <= parallel_in;
      bit_cnt <= 0;
      serial_out <= parallel_in;  // LSB first
    end else begin
      serial_out <= data_reg[bit_cnt+1];
      bit_cnt <= bit_cnt + 1;
    end
  end
endmodule

// RX CDR + 1:32 deserializer
module serdes_rx_1to32 (
  input clk_ref, serial_in,
  output reg [31:0] parallel_out,
  output reg clk_1x
);

Conceptually, SerDes shrinks motherboard pin counts from 128+ to <10 by multiplexing bits at 56-112Gbps/lane, validated by BERT stressing DUT through backplanes—PRBS31 patterns confirm CTLE/DFE convergence while CDR locks phase. Powers DisplayPort UHBR20 and USB4 tunneling, where gearbox adapts 64b/66b Ethernet to 256b/257b PCIe encoding for protocol bridges.

/ˌdiː juː ˈtiː/

n. "Electronic component or system currently undergoing validation by BERT or oscilloscope against specifications."

DUT, short for Device Under Test, refers to any hardware (chip, board, cable assembly, or full system) actively probed during characterization, compliance validation, or production testing—connected to test equipment like BERTs, oscilloscopes, or protocol analyzers measuring performance against datasheet guarantees. In SerDes validation, DUT receives stressed PRBS patterns through channel impairments, with RX eye diagrams and BER logged via loopback or golden PLL modes.

Key characteristics of DUT include: Test Fixture Integration via pogo pins/bed-of-nails or SMPM coax for SMA breakouts; Loopback Mode shorts TX→RX internally for self-contained PHY validation; Golden Reference compares against characterized path loss/insertion; Fixture De-embedding removes test board effects from raw S-parameters; Production ATE scales single-DUT probing to 1000s/hour via handler interface.

Conceptual example of DUT usage:

# Python ATE script characterizing SerDes DUT
import pyvisa
import numpy as np

# Connect BERT to DUT SerDes RX via SMA
bert = pyvisa.ResourceManager().open_resource('TCPIP::BERT_IP::INSTR')
scope = pyvisa.ResourceManager().open_resource('TCPIP::SCOPE_IP::INSTR')

# Stress DUT with PRBS31 + 14.1dB loss
bert.write(':CHAN:LOSS 14.1')      # Backplane emulation
bert.write(':PAT:TYPE PRBS31')     # LFSR pattern
bert.write(':TEST:BITS 1e12')      # 1Tbit test time
bert.write(':TEST:START')

# Measure RX eye on scope
scope.write(':MEAS:EYE:HEIGHT?')   # 200mV min spec
eye_height = float(scope.query())
scope.write(':MEAS:BER? 1e-6')     # Projected BER

print(f"DUT RX eye: {eye_height}mV, BERT: {bert.query(':TEST:BER?')}")

# Pass/fail vs USB4 spec
assert eye_height > 180e-3 and float(bert.query(':TEST:BER?')) < 1e-12

Conceptually, DUT transforms from silicon prototype to validated product when stressed by PRBS through CTLE-equipped channels—BERT counts errors while VNA characterizes Sdd21/Sscd21 margins. Production handlers robotically dock 1000s DUT/hour into ATE sockets, where parametric specs (eye=180mV min, BER=1e-12) gate shipments; contrasts SUT (full system) by isolating PHY silicon pre-board spin. Indispensable for USB4, DisplayPort, PCIe Gen6 qualification hitting bathtub Q>15dB margins.

/eɪtʃ diː aɪ ɛm aɪ/

n. "Proprietary audio/video interface carrying TMDS streams with CEC unlike royalty-free DisplayPort."

HDMI, short for High-Definition Multimedia Interface, transmits uncompressed video, multi-channel audio, and control data over TMDS lanes (HDMI2.1=48Gbps), supporting 10K@120Hz with DSC, ARC/eARC return audio, and CEC device control across Type-A/D/Mini/Micro connectors. Unlike DVI's video-only limitation, HDMI embeds DD++/EDID, Consumer Electronics Control (CEC=BraviaSync), and Audio Return Channel (ARC) in blanking intervals, with licensing fees funding HDMI Forum evolution contrasting VESA's open DisplayPort.

Key characteristics of HDMI include: TMDS Encoding 8b→10b like DVI but with audio/infoframes (HDMI2.1=12/24Gbps TMDS x3 lanes); HDR10/HLG/Dolby Vision dynamic metadata; eARC bidirectional 37Mbps uncompressed audio (Dolby TrueHD); Variable Refresh Rate (VRR=FreeSync); Source-Based Tone Mapping for mismatched dynamic range; Ultra High Speed cables mandatory for 48Gbps (48Gbps active optical).

Conceptual example of HDMI usage:

/* HDMI 2.1 Source InfoFrame packet for 4K@120Hz HDR */
struct hdmi_infoframe {
    uint8_t type = 0x87;          // AVI InfoFrame
    uint8_t version = 0x02;
    uint8_t length = 0x0D;
    uint8_t checksum;
    
    // Video ID Code (VIC) for 4K120
    uint8_t vic = 97;             // 3840x2160@120Hz
    uint8_t pixel_repeat = 0;
    
    // Colorimetry + Dynamic Range
    uint8_t colorimetry = 0x04;   // BT.2020
    uint8_t dynamic_range = 0x01; // HDR Static Metadata Type 1
} avi_if;

void hdmi_send_infoframe(struct hdmi_infoframe *ifp) {
    calculate_checksum(ifp);
    tmds_insert_during_blanking(ifp, HDMI_PACKET_PERIOD);
}

Conceptually, HDMI bundles pixel clock+TMDS data lanes with sideband packets during blanking (like DisplayPort MSA but HDMI-licensed), tunneling through USB4 ALT mode while CEC chains Blu-ray→soundbar→TV control. HDMI2.1 FRL (Fixed Rate Link) replaces TMDS for 48Gbps, stress-tested via PRBS patterns hitting receiver CTLE/DFE, with Ultra High Speed cables ensuring 1e-12 BER unlike passive copper limits plaguing early HDMI2.0 18Gbps deployments.

/ˌdiː ɛs ˈsiː/

n. "VESA's visually lossless video compression enabling 8K@60Hz over DisplayPort HBR3 bandwidth limits."

DSC, short for Display Stream Compression, is a low-latency compression algorithm developed by VESA that achieves 3:1 ratios using DPCM prediction, YCoCg-R color transform, and entropy coding on pixel slices, enabling 4K@144Hz/8K@60Hz over existing DisplayPort 1.4 (25.92Gbps) and HDMI 2.1 links without perceptible artifacts. Processes frames in real-time (sub-microsecond latency) by dividing into independent slices (1/3-1/4 frame width), quantizing residuals after intra prediction—mandatory for USB4 UHBR20 tunnels exceeding raw pixel clocks.

Key characteristics of DSC include: Visually Lossless 3:1 compression (119Gbps 8K@60 → 40Gbps) imperceptible at normal viewing distances; Zero Latency real-time encoding/decoding (<1μs end-to-end); Slice-Based parallel processing of 1/3 frame widths with independent headers; YCoCg-R Color optimal for luma/chroma separation unlike RGB quantization; Rate Control maintains constant bitrate via qp adjustment without buffering.

Conceptual example of DSC usage:

/* DSC 1.2a encoder slice processing */
typedef struct {
    uint32_t slice_width;    // 1/3 frame width (e.g. 1280 for 3840x2160)
    uint32_t slice_height;   // 8-108 lines
    int qp;                  // Quantization parameter [8-17]
    bool intra_mode;         // Force all-intra slice
} dsc_slice_config;

void dsc_encode_slice(uint16_t *rgb_pixels, uint8_t *compressed) {
    // 1. YCoCg-R color transform
    int16_t y, co, cg, r;
    y  = (rgb >> 2) + (rgb >> 1) + (rgb >> 2); [youtube](https://www.youtube.com)
    co = (rgb >> 1) - (rgb >> 1);
    cg = (rgb >> 1) - (rgb >> 2); [youtube](https://www.youtube.com)
    
    // 2. DPCM prediction (left/above neighbors)
    int16_t pred_y = prev_y + left_y >> 1;
    int16_t res_y  = y - pred_y;
    
    // 3. Quantize + Huffman code
    uint8_t quant_y = res_y >> qp;
    huffman_encode(quant_y, compressed++);
    
    // 4. Repeat for Co/Cg, rate control
}

Conceptually, DSC shrinks raw pixel streams by predicting/chroma-subsampling within DisplayPort main stream attributes (MSA), enabling 4K@240Hz over DVI-era cables—slice headers negotiate compression ratio during link training alongside CTLE equalization. Decoder mirrors process instantly; gaming monitors auto-enable for VRR compatibility, stress-tested via PRBS patterns ensuring LFSR-generated video maintains 1e-12 BER through compressed pipeline.

/ˌdiː viː ˈaɪ/

n. "Digital video interface transmitting uncompressed TMDS pixel streams as DisplayPort's analog predecessor."

DVI, short for Digital Visual Interface, delivers uncompressed digital video via TMDS (Transition-Minimized Differential Signaling) over 1-2 data pairs (Single-Link=3.96Gbps, Dual-Link=7.92Gbps), supporting 1920x1200@60Hz single/2560x1600@60Hz dual without audio or daisy-chaining unlike modern DisplayPort. Developed by DDWG in 1999 as VGA successor, DVI-D (digital-only), DVI-I (integrated analog/digital), and DVI-A variants bridge CRT-to-LCD transition via 24-pin connectors with optional 5-pin VGA breakout.

Key characteristics of DVI include: TMDS Encoding transitions 8b→10b symbols minimizing EMI (max 165MHz pixel clock single-link); Single/Dual-Link versions double bandwidth via second TMDS pair for QXGA+ resolutions; DVI-D/DVI-I/DVI-A connector variants with 18/24 digital + 0/4/5 analog pins; No Audio/EDID2/hot-plug limitations vs HDMI/DP packetized protocols; Screw-lock mounting ensures desktop stability absent in USB-C ecosystems.

Conceptual example of DVI usage:

-- DVI TMDS encoder behavioral model (10-bit symbol generation)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tmds_encoder is
  port (
    clk   : in  std_logic;
    din   : in  std_logic_vector(7 downto 0);  -- 8-bit pixel data
    dout  : out std_logic_vector(9 downto 0)   -- 10-bit TMDS symbol
  );
end entity;

architecture behavioral of tmds_encoder is
  function count_ones(d : std_logic_vector) return integer is
  begin
    return count_ones(to_integer(unsigned(d)));
  end function;
  
begin
  process(clk)
    variable ones : integer;
  begin
    if rising_edge(clk) then
      ones := count_ones(din);
      if ones > 4 or (ones = 4 and din(7) = '1') then
        dout <= std_logic_vector(to_unsigned(ones*2 - 10, 10));  -- XOR invert
      else
        dout <= std_logic_vector(to_unsigned(10 - ones*2, 10)); -- No invert
      end if;
    end if;
  end process;
end architecture;

Conceptually, DVI blasts raw pixel clock+data through TMDS pairs with fixed 0.5UI eye openings, requiring clean 24AWG cables under 5m unlike USB4 retimers—link training absent forces graphics cards to guess voltage swing unlike DisplayPort LTK. Stress-tested via PRBS generators hitting TMDS receivers with CTLE compensation, now legacy in HDMI/DP era but immortalized in workstation GPUs tunneling through active adapters to 4K@30Hz max.

/ˈdɪspleɪ pɔːrt/

n. "VESA's royalty-free digital audio/video interface transmitting uncompressed pixel streams over HBR/UHBR lanes."

DisplayPort, short for DisplayPort, delivers high-bandwidth digital video/audio via 1-4 differential pairs (HBR3=32.4Gbps, UHBR20=80Gbps), supporting daisy-chaining, Multi-Stream Transport (MST) for 4x 1080p monitors, and Adaptive Sync (FreeSync). Tunnels through USB4 and competes with HDMI via 128b/132b encoding (DP2.1), enabling 16K@60Hz or 8K@240Hz with DSC compression—uses micro-packet architecture with link training unlike DVI's TMDS.

Key characteristics of DisplayPort include: Micro-Packet Architecture transmits blanking/aux data separately from pixels (HBR3=8.1Gbps/lane x4); UHBR Tiers scale from 10/13.5/20Gbps per lane (DP2.1=77.37Gbps payload); Multi-Stream Transport fans out single cable to 3+ displays via time-division multiplexing; Adaptive-Sync eliminates tearing (FreeSync/G-Sync compatible); Daisy-Chaining connects 6+ monitors without hub using DP-in/DP-out ports.

Conceptual example of DisplayPort usage:

/* DP 2.1 Link Training - UHBR20 negotiation */
struct dp_link_training {
    uint8_t voltage_swing;      // 0-3 (400-1200mV)
    uint8_t pre_emphasis;       // 0-3 (0-3.5dB)
    uint8_t post_cursor;        // DFE taps
    bool uhbr20_trained;        // 20Gbps/lane success
};

void dp_lt_train(struct dp_link_training *lt) {
    // Training Pattern 1: Swing/emphasis sweep
    for (lt->voltage_swing = 0; swing < 4; swing++) {
        send_tp1_pattern();
        if (rx_eq_satisfied()) break;
    }
    // TP2: Channel equalization with DFE
    send_tp2_pattern();
    lt->uhbr20_trained = check_ber_lt_1e-8();
    
    // Final: Main stream attributes (MSA)
    set_msa(3840, 2160, 60, 8);  // 4K@60 8bpc
}

Conceptually, DisplayPort streams raw RGB pixels + audio + sideband messages over HBR/UHBR lanes with link training optimizing CTLE/DFE taps per cable length—MST branches one PHY to office monitor daisy-chain while USB4 tunnels DP1.4 inside 40Gbps pipe for laptop docking. Stress-tested via PRBS/LFSR generators hitting 1e-12 BER, with DP80 cables mandatory for UHBR20 unlike HDMI's license walls.