/ˈvɛrɪlɒɡ/
noun — "hardware description language for digital design."
Verilog is a hardware description language (HDL) used to model, simulate, and synthesize digital systems such as integrated circuits, microprocessors, FPGAs, and ASICs. It allows designers to describe hardware behavior, timing, and structure in a textual form, bridging the gap between software-like design and actual hardware implementation. Verilog supports both behavioral and structural modeling, enabling engineers to write high-level algorithmic representations or low-level gate-level descriptions.
Technically, Verilog enables designers to define modules that contain input and output ports, internal signals, and logic operations. Modules can be instantiated hierarchically to build complex digital systems. The language provides constructs for sequential logic (e.g., always blocks), combinational logic, finite state machines, and concurrency, allowing simulation of timing and parallel hardware execution. Tools such as simulators and synthesis engines interpret Verilog to verify behavior and generate bitstreams for FPGAs or gate-level netlists for ASICs.
# simple 4-bit counter in Verilog
module counter(input clk, input rst, output reg [3:0] count);
always @(posedge clk or posedge rst) begin
if (rst)
count <= <em>0</em>;
else
count <= count + <em>1</em>;
end
endmodule
Operationally, Verilog is used in embedded and digital system workflows to design hardware at a high level of abstraction. Engineers write and simulate designs to check functionality, timing, and performance before synthesizing them onto an FPGA or producing an ASIC. It enables rapid prototyping, verification, and iterative development without modifying physical hardware.
Conceptually, Verilog is like a programming language for circuits: instead of writing software for a CPU, you describe how the wires, gates, and flip-flops behave. Simulation then “executes” your hardware design in a virtual environment to ensure correctness.
See FPGA, HDL, ASIC, Simulation, Digital Logic.