/ˈpɛɪdʒd ˈmɛməri ˈmænɪdʒmənt ˈjuːnɪt/
noun — "hardware that translates virtual pages into physical memory."
PMMU, short for Paged Memory Management Unit, is a hardware component responsible for implementing paged virtual memory by translating virtual addresses used by software into physical memory addresses used by the hardware. It sits between the CPU and main memory, enforcing memory isolation, access control, and address translation on every memory reference made by a running program.
Technically, a PMMU operates by dividing memory into fixed-size blocks called pages. Virtual memory is organized into virtual pages, while physical memory is divided into page frames of the same size. When the CPU issues a memory access, the PMMU intercepts the virtual address and translates it into a physical address using page tables maintained by the Operating System. This translation happens transparently and at hardware speed, allowing programs to operate as if they have access to a large, contiguous memory space.
The core data structure used by a PMMU is the page table. Each page table entry maps a virtual page number to a physical frame number and includes control bits that describe permissions and state. These bits typically indicate whether the page is readable, writable, executable, present in memory, or accessed recently. If a virtual page is not present in physical memory, the PMMU triggers a page fault, transferring control to the operating system so it can load the required page from secondary storage.
Because page table lookups would be too slow if performed directly in memory for every access, most PMMUs include a Translation Lookaside Buffer (TLB). The TLB is a small, fast cache that stores recent virtual-to-physical translations. When a translation is found in the TLB, address resolution completes in a few CPU cycles. When it is not found, a page table walk is performed, and the result may be inserted into the TLB for future use.
A PMMU plays a critical role in process isolation and system security. Each process typically has its own page tables, preventing one process from accessing the memory of another unless explicitly permitted. This isolation allows multitasking systems to run untrusted or faulty programs without risking corruption of the kernel or other applications. Access violations detected by the PMMU result in hardware exceptions, which the operating system handles as segmentation faults or access violations.
In multiprocessor systems, the PMMU must also cooperate with cache coherence and context switching mechanisms. When the scheduler switches from one process to another, the active page tables change. The PMMU must either flush or selectively invalidate TLB entries to ensure that stale translations from the previous process are not reused. Some architectures support address space identifiers to reduce the cost of these transitions.
Historically, the PMMU evolved from simpler memory management units that supported only segmentation or fixed relocation. Paging-based designs proved more flexible and scalable, especially as systems grew to support large address spaces and fine-grained protection. Modern CPUs typically integrate the PMMU directly into the processor core, making virtual memory a fundamental architectural feature rather than an optional add-on.
Conceptually, a PMMU acts like a dynamic map between a program’s imagined memory layout and the machine’s actual physical memory. Programs follow the map without knowing where things really live, while the hardware ensures that every access lands in the correct place or is safely blocked if it should not occur.
See Virtual Memory, Memory Management Unit, Page Replacement, Operating System.