Component

/ˌɪnˌpʊt ˌaʊtˈpuː mɛməri ˈmænɪdʒmənt ˈjuːnɪt/

noun — "translates and protects device memory access."

IOMMU, short for Input-Output Memory Management Unit, is a specialized hardware component that manages memory access for peripheral devices, translating device-generated addresses into physical addresses in main memory and enforcing protection policies. By controlling and isolating the memory access of I/O devices, the IOMMU prevents devices from reading or writing outside their allocated memory regions, which is critical for security, system stability, and virtualization.

Technically, an IOMMU operates similarly to a CPU-side PMMU, but for devices rather than software processes. It maintains a set of page tables mapping device-visible addresses, sometimes called I/O virtual addresses, to physical memory addresses. When a device initiates a memory transaction, such as via DMA (Direct Memory Access), the IOMMU intercepts the request, performs the translation, and verifies permissions before granting access. If the transaction is invalid or exceeds assigned boundaries, the IOMMU raises a fault, protecting the system from accidental corruption or malicious behavior.

The IOMMU is essential in modern systems with virtualization. When multiple virtual machines share physical hardware, each virtual machine may have devices assigned through passthrough mechanisms. The IOMMU translates guest physical addresses into host physical addresses, ensuring that devices cannot access memory outside the guest’s allocated space. This capability is critical for technologies like Intel VT-d or AMD-Vi, which provide secure and isolated device access in virtualized environments.

Example operational scenario:

# conceptual device memory access
device_address = 0x1000  # device thinks it's writing here
physical_address = IOMMU.translate(device_address)
if IOMMU.check_permission(device, physical_address):
    memory[physical_address] = data
else:
    raise AccessViolation

In addition to protection and address translation, IOMMUs can optimize performance by remapping addresses to reduce memory fragmentation, enable page-level caching policies for devices, and provide hardware support for interrupt remapping. Many high-performance peripherals, including GPUs, network cards, and storage controllers, rely on the IOMMU to safely perform high-bandwidth DMA operations without risk to the host system.

Conceptually, an IOMMU is like a security checkpoint and translator for device memory requests. Devices operate under the assumption that they have direct memory access, but the IOMMU ensures that every request lands in the correct location and adheres to access rules, preventing collisions, corruption, or leaks between devices and the system.

See PMMU, DMA, Virtual Memory, Operating System.

/ˈpɛɪdʒd ˈmɛməri ˈmænɪdʒmənt ˈjuːnɪt/

noun — "hardware that translates virtual pages into physical memory."

PMMU, short for Paged Memory Management Unit, is a hardware component responsible for implementing paged virtual memory by translating virtual addresses used by software into physical memory addresses used by the hardware. It sits between the CPU and main memory, enforcing memory isolation, access control, and address translation on every memory reference made by a running program.

Technically, a PMMU operates by dividing memory into fixed-size blocks called pages. Virtual memory is organized into virtual pages, while physical memory is divided into page frames of the same size. When the CPU issues a memory access, the PMMU intercepts the virtual address and translates it into a physical address using page tables maintained by the Operating System. This translation happens transparently and at hardware speed, allowing programs to operate as if they have access to a large, contiguous memory space.

The core data structure used by a PMMU is the page table. Each page table entry maps a virtual page number to a physical frame number and includes control bits that describe permissions and state. These bits typically indicate whether the page is readable, writable, executable, present in memory, or accessed recently. If a virtual page is not present in physical memory, the PMMU triggers a page fault, transferring control to the operating system so it can load the required page from secondary storage.

Because page table lookups would be too slow if performed directly in memory for every access, most PMMUs include a Translation Lookaside Buffer (TLB). The TLB is a small, fast cache that stores recent virtual-to-physical translations. When a translation is found in the TLB, address resolution completes in a few CPU cycles. When it is not found, a page table walk is performed, and the result may be inserted into the TLB for future use.

A PMMU plays a critical role in process isolation and system security. Each process typically has its own page tables, preventing one process from accessing the memory of another unless explicitly permitted. This isolation allows multitasking systems to run untrusted or faulty programs without risking corruption of the kernel or other applications. Access violations detected by the PMMU result in hardware exceptions, which the operating system handles as segmentation faults or access violations.

In multiprocessor systems, the PMMU must also cooperate with cache coherence and context switching mechanisms. When the scheduler switches from one process to another, the active page tables change. The PMMU must either flush or selectively invalidate TLB entries to ensure that stale translations from the previous process are not reused. Some architectures support address space identifiers to reduce the cost of these transitions.

Historically, the PMMU evolved from simpler memory management units that supported only segmentation or fixed relocation. Paging-based designs proved more flexible and scalable, especially as systems grew to support large address spaces and fine-grained protection. Modern CPUs typically integrate the PMMU directly into the processor core, making virtual memory a fundamental architectural feature rather than an optional add-on.

Conceptually, a PMMU acts like a dynamic map between a program’s imagined memory layout and the machine’s actual physical memory. Programs follow the map without knowing where things really live, while the hardware ensures that every access lands in the correct place or is safely blocked if it should not occur.

See Virtual Memory, Memory Management Unit, Page Replacement, Operating System.

/ˈskɛdʒʊlər/

noun — "decides which task runs when."

Scheduler is a core component of an operating system responsible for allocating CPU time and other resources among competing processes or threads. It determines the order and duration of execution, aiming to optimize system performance, responsiveness, fairness, or real-time constraints depending on the policy employed. The scheduler operates at multiple levels, including long-term, medium-term, and short-term scheduling, each focusing on different aspects of resource management.

Technically, a scheduler uses data structures such as queues, priority lists, and timing mechanisms to track ready and waiting tasks. Long-term scheduling controls the admission of new processes into the system, balancing workload and memory usage. Medium-term scheduling temporarily suspends and resumes processes to optimize CPU utilization and memory allocation. Short-term scheduling, or CPU scheduling, selects which ready process receives the CPU next, often using algorithms like First-Come-First-Served (FCFS), Shortest Job Next (SJN), Round-Robin (RR), or Least Recently Used-inspired variants for resource-sensitive contexts.

Schedulers may be preemptive or non-preemptive. In preemptive scheduling, a running process can be interrupted and replaced by a higher-priority task or based on a time slice expiration. Non-preemptive scheduling allows a process to run until it voluntarily yields or completes, reducing context switch overhead but potentially causing starvation. The operating system maintains a process control block (PCB) containing scheduling-related metadata such as priority, execution time, and state, which the scheduler references when making decisions.

Example conceptual flow of CPU scheduling:

while system has ready processes:
    select process based on policy
    allocate CPU for time slice
    if process completes or yields:
        update state
    else if time slice expires:
        preempt and requeue

Operationally, the scheduler affects throughput, latency, fairness, and responsiveness. In desktop environments, it ensures interactive applications respond promptly. In real-time systems, it enforces strict deadlines to prevent missed timing constraints. In multiprocessor or multicore systems, the scheduler also manages load balancing, affinity, and cache locality to maximize parallel efficiency.

Advanced schedulers incorporate heuristics, dynamic priority adjustments, and aging to prevent starvation and optimize for specific workloads. In virtualized environments, hypervisors implement additional scheduling layers to manage CPU allocation across multiple virtual machines.

Conceptually, the scheduler is like a traffic controller for the CPU, deciding which vehicle (process or thread) moves through the intersection at any moment to maintain order, efficiency, and fairness in a complex system.

See Process, Thread, CPU, Operating System, LRU.

/ˈmɛməri ˈmænɪdʒmənt ˈjuːnɪt/

noun — "hardware that translates and protects memory."

Memory Management Unit is a hardware component of a processor responsible for translating virtual memory addresses into physical memory addresses and enforcing memory protection rules. It sits between the CPU core and physical memory, acting as the gatekeeper that ensures programs see a consistent, isolated view of memory while preventing illegal or unsafe access.

Technically, the memory management unit performs address translation using data structures such as page tables or segment tables. When a program issues a memory access, it produces a virtual address. The MMU consults the current translation context, typically defined by the operating system, to map that virtual address to a physical address. This mapping is often accelerated using a Translation Lookaside Buffer (TLB), a small cache that stores recent address translations to avoid repeated page table walks.

The MMU is also responsible for enforcing access permissions. Each memory region can be marked as readable, writable, executable, or inaccessible. If a program attempts an operation that violates these permissions, the MMU raises a fault, such as a segmentation fault or access violation, allowing the operating system to intervene. This mechanism underpins process isolation, memory safety, and modern security features such as non-executable memory regions.

Operationally, the memory management unit enables virtual memory by allowing only a subset of a process’s address space to be resident in physical memory at any given time. When a referenced page is not present, the MMU signals a page fault. The operating system then loads the required page from secondary storage and updates the page tables so the MMU can complete the translation. This collaboration between hardware and software allows systems to efficiently multiplex memory across many processes.

A simplified conceptual flow looks like this:

virtual_address
    → TLB lookup
        if hit:
            physical_address
        else:
            page_table_walk
                if valid:
                    update TLB
                    physical_address
                else:
                    raise page_fault

In practice, MMU design has a significant impact on system performance and scalability. Features such as multi-level page tables, huge pages, and tagged TLBs reduce translation overhead for large address spaces. In multiprocessor systems, the MMU must also support context switching, ensuring that each process’s address mappings are isolated while allowing controlled sharing of memory where required.

The memory management unit is not exclusive to general-purpose CPUs. GPUs, network processors, and embedded systems often include MMUs or simpler memory protection units to support isolation and controlled access. In constrained embedded environments, a reduced MMU may provide protection without full virtual memory, balancing safety with hardware simplicity.

Conceptually, the memory management unit is like a highly vigilant librarian who translates a reader’s catalog numbers into exact shelf locations while enforcing strict rules about which sections each reader is allowed to access.

See Virtual Memory, Page Replacement, Operating System, Cache.

/ˌsiː piː ˈjuː/

noun — "central processor executing instructions."

CPU, short for Central Processing Unit, is the primary component of a computer responsible for executing program instructions, performing arithmetic and logical operations, and coordinating the activities of all other hardware components. It functions as the “brain” of a computing system, interpreting and processing data according to software commands.

Technically, a CPU consists of multiple key units:

• Arithmetic Logic Unit (ALU): Performs arithmetic operations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT).
• Control Unit (CU): Directs data flow between memory, input/output devices, and the ALU, decoding instructions from programs and issuing commands.
• Registers: Small, fast storage locations inside the CPU for temporary storage of data, addresses, and intermediate results.
• Cache Memory: High-speed memory close to the CPU for storing frequently accessed instructions and data to reduce latency.

Operationally, the CPU follows the fetch-decode-execute cycle:

• Fetch: Retrieves an instruction from memory (RAM) at the address indicated by the program counter.
• Decode: Interprets the instruction to determine the required operation and operands.
• Execute: Performs the operation using the ALU or control unit, writing results back to registers or memory.
• Advance: Updates the program counter to the next instruction.

Example conceptual workflow in pseudo-code:

while (program_counter < program_length):
    instruction = memory[program_counter]
    decoded = decode(instruction)
    result = ALU_execute(decoded)
    registers[decoded.destination] = result
    program_counter += 1

CPUs vary in architecture, including single-core, multi-core, and specialized designs for performance or energy efficiency. Modern CPUs may include integrated graphics processing capabilities, multiple levels of cache (L1, L2, L3), and support for advanced instruction sets (SSE, AVX) to accelerate computational workloads.

Conceptually, a CPU is like the conductor of an orchestra: it reads the musical score (program instructions), directs the musicians (hardware components) to perform their parts, and ensures the resulting performance (system operation) is synchronized and accurate.

See GPU, Cache, ALU, Registers.

/kənˈtroʊl ˈjuːnɪt/

noun … “CPU component that directs operations.”

Control Unit is a central part of a CPU or microprocessor responsible for managing and coordinating the execution of instructions. It interprets instructions from memory, generates control signals, and orchestrates the operation of the ALU, Registers, and other components to ensure correct timing and sequencing.

Key characteristics of Control Unit include:

• Instruction decoding: determines what action each instruction requires.
• Signal generation: issues control signals to other CPU components.
• Timing coordination: synchronizes operations using the system clock.
• Execution flow management: handles sequencing, branching, and program counters.
• Interaction with memory and I/O: manages data transfer between CPU and peripherals.

Applications of Control Unit include executing program instructions, managing arithmetic and logic operations, controlling data paths, and coordinating input/output processes.

Workflow example: Fetch-decode-execute cycle:

instruction = memory.fetch(pc)
decoded = control_unit.decode(instruction)
control_signals = control_unit.generate(decoded)
ALU.execute(control_signals, operands)

Here, the control unit interprets instructions, issues the proper signals, and ensures the ALU and registers perform the correct operations.

Conceptually, a Control Unit is like the conductor of an orchestra: it ensures that each component performs its role at the correct time, producing correct and harmonious system behavior.

See CPU, ALU, Register, Control Logic, Microprocessor.

/ˈɛnərdʒi ˈstɔːrɪdʒ/

noun … “Capturing energy for later use.”

Energy Storage refers to the methods and systems used to capture energy produced at one time and release it when needed, ensuring a steady supply despite variable demand or intermittent generation. Energy can be stored in electrical, chemical, mechanical, or thermal forms, and energy storage is critical for balancing supply and demand in power grids, renewable energy systems, and portable devices.

Key characteristics of Energy Storage include:

• Forms: chemical (batteries, fuel cells), mechanical (flywheels, compressed air), electrical (capacitors, supercapacitors), thermal (molten salts, phase-change materials).
• Capacity: total energy that can be stored, measured in joules (J) or kilowatt-hours (kWh).
• Power rating: rate at which stored energy can be delivered.
• Efficiency: ratio of energy output to input, accounting for losses.
• Applications: grid stabilization, renewable energy integration, electric vehicles, portable electronics, and backup power systems.

Workflow example: Charging a battery:

battery = Battery(capacity=100)   -- 100 Wh
power_source = 50                     -- watts
time_hours = battery.capacity / power_source
battery.charge(time_hours)

Here, energy is stored chemically in the battery and can be discharged later to power devices.

Conceptually, Energy Storage is like a reservoir: it holds energy until it is needed and releases it in controlled amounts to maintain system operation.

See Battery, Capacitor, Power, Electricity, Energy.

/kənˈtroʊl ˈlɑːdʒɪk/

noun … “Circuitry that directs operations in digital systems.”

Control Logic is the part of a CPU or digital system responsible for orchestrating the flow of data, managing instruction execution, and coordinating the operation of various components such as the ALU, Registers, and memory. It interprets instructions, generates timing signals, and ensures that each part of the system performs the correct operation at the right time.

Key characteristics of Control Logic include:

• Instruction decoding: determines the operation to perform based on the instruction set.
• Signal generation: produces control signals for registers, ALU, memory, and I/O devices.
• Timing management: synchronizes operations using clock signals.
• Sequential or combinational design: can involve both logic types to manage system states.
• Critical for CPU operation: ensures correct execution order and prevents conflicts.

Applications of Control Logic include managing instruction cycles in processors, controlling data paths in digital circuits, implementing finite-state machines, and coordinating peripheral devices.

Workflow example: Executing an ADD instruction:

instruction = fetch(pc)
decoded = control_logic.decode(instruction)
control_signals = control_logic.generate(decoded)
ALU.execute(control_signals, operands)

Here, the control logic interprets the instruction, issues control signals, and coordinates the ALU and registers to perform the operation.

Conceptually, Control Logic is like a conductor in an orchestra: it ensures that every component plays its part at the right time to produce correct and harmonious operation.

See CPU, ALU, Register, Sequential Circuit, Finite-State Machine.

/ˈrɛdʒɪstər/

noun … “Small, fast storage inside a CPU.”

Register is a tiny, high-speed storage location within a CPU or microprocessor used to hold data, instructions, or addresses temporarily during processing. Registers allow the CPU to access and manipulate information much faster than using main memory, making them essential for instruction execution, arithmetic operations, and control flow.

Key characteristics of Register include:

• Speed: extremely fast compared to RAM or cache.
• Size: typically small, storing a few bytes or words, depending on CPU architecture.
• Types: general-purpose, special-purpose (e.g., program counter, stack pointer), and status registers.
• Temporary storage: holds operands, results, and addresses for immediate processing.
• Integral to instruction execution: works closely with the ALU and control unit.

Applications of Register include storing intermediate computation results, tracking program execution, passing parameters, and addressing memory locations efficiently.

Workflow example: Adding two values using registers:

R1 = 5
R2 = 7
R3 = ALU.add(R1, R2)
print(R3)   -- 12

Here, the registers temporarily hold operands and store the result for further processing.

Conceptually, a Register is like a notepad on a worker’s desk: small, fast, and convenient for holding information that is actively being used.

See CPU, ALU, Memory, Microprocessor, Cache.

/ˌeɪ ɛl ˈjuː/

noun … “Circuit that performs arithmetic and logic operations.”

ALU, short for Arithmetic Logic Unit, is a fundamental component of a CPU or microprocessor that executes mathematical calculations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, XOR). The ALU processes binary data from registers or memory and outputs the result to registers, memory, or other parts of the system.

Key characteristics of ALU include:

• Arithmetic operations: addition, subtraction, multiplication, division.
• Logical operations: AND, OR, NOT, XOR, comparison operations.
• Bitwise operations: shift left, shift right, rotate.
• Integration: works with control unit, registers, and memory to execute instructions.
• Width: defined by the number of bits it can process simultaneously (e.g., 8-bit, 32-bit, 64-bit).

Applications of ALU include executing CPU instructions, performing calculations in microcontrollers, signal processing, and computer graphics operations.

Workflow example: Adding two binary numbers:

operand1 = 0b1010   -- 10
operand2 = 0b0111   -- 7
result = ALU.add(operand1, operand2)
print(result)       -- 0b10001 (17)

Here, the ALU adds two binary operands and outputs the sum.

Conceptually, an ALU is like the brain’s calculator: it takes inputs, performs defined operations, and delivers precise results to the system.

See CPU, Microprocessor, Registers, Control Unit, Binary.