/ˈmɛməri ˈmænɪdʒmənt ˈjuːnɪt/
noun — "hardware that translates and protects memory."
Memory Management Unit is a hardware component of a processor responsible for translating virtual memory addresses into physical memory addresses and enforcing memory protection rules. It sits between the CPU core and physical memory, acting as the gatekeeper that ensures programs see a consistent, isolated view of memory while preventing illegal or unsafe access.
Technically, the memory management unit performs address translation using data structures such as page tables or segment tables. When a program issues a memory access, it produces a virtual address. The MMU consults the current translation context, typically defined by the operating system, to map that virtual address to a physical address. This mapping is often accelerated using a Translation Lookaside Buffer (TLB), a small cache that stores recent address translations to avoid repeated page table walks.
The MMU is also responsible for enforcing access permissions. Each memory region can be marked as readable, writable, executable, or inaccessible. If a program attempts an operation that violates these permissions, the MMU raises a fault, such as a segmentation fault or access violation, allowing the operating system to intervene. This mechanism underpins process isolation, memory safety, and modern security features such as non-executable memory regions.
Operationally, the memory management unit enables virtual memory by allowing only a subset of a process’s address space to be resident in physical memory at any given time. When a referenced page is not present, the MMU signals a page fault. The operating system then loads the required page from secondary storage and updates the page tables so the MMU can complete the translation. This collaboration between hardware and software allows systems to efficiently multiplex memory across many processes.
A simplified conceptual flow looks like this:
virtual_address
→ TLB lookup
if hit:
physical_address
else:
page_table_walk
if valid:
update TLB
physical_address
else:
raise page_fault
In practice, MMU design has a significant impact on system performance and scalability. Features such as multi-level page tables, huge pages, and tagged TLBs reduce translation overhead for large address spaces. In multiprocessor systems, the MMU must also support context switching, ensuring that each process’s address mappings are isolated while allowing controlled sharing of memory where required.
The memory management unit is not exclusive to general-purpose CPUs. GPUs, network processors, and embedded systems often include MMUs or simpler memory protection units to support isolation and controlled access. In constrained embedded environments, a reduced MMU may provide protection without full virtual memory, balancing safety with hardware simplicity.
Conceptually, the memory management unit is like a highly vigilant librarian who translates a reader’s catalog numbers into exact shelf locations while enforcing strict rules about which sections each reader is allowed to access.
See Virtual Memory, Page Replacement, Operating System, Cache.